The present invention relates to memory testing in a data processing system.
Memory is an important component of computers, and its properties, such as compatibility, running speed, stability, and the like, play an important role in computer quality. As the demand of data processing capability continues to increase, memory has been playing an unprecedented role in computing industry. Memory subsystems with larger sizes and more advanced silicon technology lead to higher demand and heavier burden on memory testing.
On one hand, larger memory size results in broader test coverage. On the other hand, advancements in silicon fabrication process technology make memory devices more vulnerable to failure, which requires stricter memory testing, with more test loops and different test patterns, to ensure system reliability.
The effort required for memory testing is proportional to memory size and test loop count. The size of memory in computers is continuously increasing, and the same is true for test loop counts. Memory testing has become a major burden of system boot performance. From the perspective of accessibility and serviceability, system boot performance is critical for servers, in terms of availability and serviceability. Consequently, a tension exists in that memory subsystems need stricter and broader memory testing, but such memory testing can degrade server boot efficiency.
XEON® is a brand of processors available from Intel Corporation targeted to servers and advanced workstations. As with the Pentium® series, the Xeon brand has been maintained over several generations of processor architectures. Older models added the Xeon moniker to the end of their corresponding names in Pentium series (such as, Pentium II Xeon), but more recent models used the name Xeon on its own. Servers with Xeon processors generally support a very large amount of memory.
The memory controller of a server with a Xeon processor provides hardware-based memory testing. The basic input/output system (BIOS) can specify a test pattern, and the memory controller performs testing based on the pattern. If a test failure happens, it can be detected by the BIOS and can be reported to the memory controller to isolate the failed device. In order for more reliability and integrity, as the existing BIOS memory test solution, more memory test loops can be executed, with each loop using the same pattern. More test loop count means more reliability, but less system performance Currently, a common compromise for such BIOS memory testing is to perform one loop, or an arbitrary loop count, of hardware memory testing, with a random or arbitrary test pattern, as a balance between reliability and performance.